1. Field of the Invention
The present invention is related to integrated circuit (IC) design and more particularly, to optimizing standard cell design configurations.
2. Background Description
Semiconductor technology and chip manufacturing advances have resulted in a steady increase of on-chip clock frequencies, the number of transistors on a single chip and the die size itself, coupled with a corresponding decrease in chip supply voltage and chip feature size. Generally, all other factors being constant, the power consumed by a given clocked unit increases linearly with the frequency of switching within it. Thus, not withstanding the decrease of chip supply voltage, chip power consumption has increased as well. Both at the chip and system levels, cooling and packaging costs have escalated as a natural result of this increase in chip power. For low end systems (e.g., handhelds, portable and mobile systems), where battery life is crucial, net power consumption reduction is important but, must be achieved without degrading performance below acceptable levels.
Consequently, power consumption has been a major design consideration for designing very large scale integrated circuits (VLSI) such as high performance microprocessors. In particular, increasing power requirements run counter to the low end design goal of longer battery life. Since chip power is directly proportion to the square of supply voltage (Vdd), reducing supply voltage is one of the most effective ways to reduce the power consumption, both active and standby (leakage) power, which is becoming more and more of a problem as technology features scale into nanometer (nm) dimension range.
While reducing supply voltage is attractive to reduce the power consumption, reducing Vdd increases transistor and gate delay. Thus, for a design that is performance constrained, the supply voltage may not be lowered too much and, it is usually determined by the most timing critical paths. However, it is often the case that most cells in a chip are timing non-critical. If those timing non-critical cells are properly selected to be on lower supply voltage(s), significant power saving may be achieved without degrading the overall circuit performance. So, One approach to reducing power is to use multiple supply voltages, each supplying different circuit blocks or voltage islands. Each voltage island runs at its minimum necessary supply voltage. Level converters are included, at least to interface lower supply voltage islands with higher supply voltage islands. The traditional level converter is a simple inverter between inputs to a differential amplifier and require both power supplies.
Unfortunately, level converters add to overhead, increasing chip power and each takes up space decreasing area available for other circuits. Level converter placement is normally restricted on a chip to the island boundaries between lower and higher supply voltage regions. This complicates the physical design for multiple supply voltage circuits because the level converters can only be physically placed in regions which have access to both power supplies. In addition, due to the differential nature of the traditional level converter circuits, the power consumption by the level converter circuits can significantly offset any power reduction possible realized by migrating to a multiple supply voltage design. Also, since these level converters add delay, this additional delay may prevent switching some circuits to the lower supply voltage, further offsetting power reduction that would otherwise be realized. Also, these differential level converters are not easily adaptable for other logic functions than a simple buffer or inverter, which might otherwise provide additional savings in delay and power.
Thus, there is a need for a level converter capable of interfacing voltage islands, each operating on a different supply voltage and that can operate on a single supply voltage.